1. Field of the Invention
The present invention relates to a pulse filter, and more particularly to a pulse filter capable of performing common-mode glitch interference cancellation in a half-bridge or full-bridge high-side driver.
2. Description of the Related Art
To describe the related art of the present invention, the relation between a pulse filter and a half-bridge or full-bridge high-side driver shall be introduced first. Please refer to FIG. 1, which shows the architecture of a typical half-bridge driver 100. As shown in FIG. 1, the typical half-bridge driver 100 at least includes a pulse generator 101, a pulse filter 102, and a latch 103.
The pulse generator 101 is used for generating a clock (CLK) signal and a complemented clock (CLKB) signal. The pulse filter 102 is used for cancelling a common-mode glitch interference accompanying the power lines of VBOOT and HBOUT, and generating a set signal and a reset signal to the latch 103. The latch 103 is used for sending a signal to a driver to switch a high-side power MOSFET. During the switching, a glitch is generated due to the capacitive characteristic of a capacitor CBOOT, i.e., the voltage difference hold between the two plates of a capacitor will not change abruptly. As a result, the certain period the capacitor takes to reach a stable state causes a glitch period. The pulse filter 102 is therefore used to deal with the glitch problem to prevent the failure of the latch 103.
One solution to eliminate the glitch interferer is to use a symmetric structure to cancel it in differential way. Please refer to FIG. 2, which shows a circuit diagram of a prior art pulse filter 300 for cancelling the common-mode glitch interferer of power lines. As shown in FIG. 2, the prior art pulse filter 300 comprises a resistor 301, a PMOS transistor 302, a PMOS transistor 303, a resistor 304, a PMOS transistor 305, a PMOS transistor 306, a resistor 307, and a resistor 308.
The pulse filter 300 comprises a pair of pull-up networks and a pair of pull-down networks. The left side pull-up network is composed of the resistor 301, the PMOS transistor 302, and the PMOS transistor 303, and the right side pull-up network is composed of the resistor 304, the PMOS transistor 305, and the PMOS transistor 306. The left side pull-down network is composed of the resistor 307, and the right side pull-down network is composed of the resistor 308.
Due to the symmetric structure, the voltage potentials at the gate and the source of the PMOS transistor 302 and the PMOS transistor 305 will change simultaneously when a glitch is produced in the power lines so that the voltage difference between the gate and the source of both transistors remain unchanged. The conduction status in each transistor, for example the PMOS transistor 302 being on and the PMOS transistor 305 being off, therefore remains unchanged too. However, the voltage potential built up at the resistor 307 will still be suppressed even though the PMOS transistor 303 is added for improving the voltage swing for the latch 103, if the glitch downs too low. This may also cause the latch 103 malfunction. Besides, the dc conducting path of the resistor 301, the transistor 302, the transistor 303, and the resistor 307 consumes a lot of power, and the resistors also occupy large die area.
As a result, the issues of voltage dropt, power consumption, and die area of a pulse filter are then tangled in the design process.
Therefore, there is a demand to provide a robust pulse filter with low power consumption that can offer great voltage swing of the set signal and the reset signal in spite of the glitch and guarantee the normal operation of the latch.